Analysis of the MIPS 32 - bit , pipelined processor using synthesized VHDL

For large and complicated ASIC designs, it is difficult to read and understand the circuits based on schematic drawings alone; as a result, a hardware description language is much needed for a succinct, descriptive, and human-readable summarization of the circuit. In this paper, we explore VHDL, a hardware description language popular in educational environment. Through the design of a 32-bits pipelined CPU as described in “Computer Organization and Design” by John L. Hennessy and David A. Patterson, we present several VHDL compilers, simulators, and synthesizers that are readily accessible for academic environments. Finally, we perform timing and area analysis the MIPS processor using Xilinx’s SPARTAN3 FPGA device and Virtex4 FPGA device. Introduction: Usually, the easiest way to understand a simple circuit is to study its schematics. From the schematics, we can derive the gate structures, wiring structures, critical paths, and more. However, as the circuits become more complicated, their schematics also become harder to understand due to the heavy amount of wires and gates crossing each other. As a result, it is imperative to find a new method to accurately describe the circuits, yet easy to understand and describe on a reasonable amount of papers. The solution for this problem lies in hardware description language (HDL).